Introduction to Implementation Generation
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[1] Rainer Leupers,et al. Time-constrained code compaction for DSPs , 1997, IEEE Trans. Very Large Scale Integr. Syst..
[2] Stephen A. Edwards. Compiling Esterel into sequential code , 2000, DAC.
[3] Song Chen,et al. Synthesis of custom interleaved memory systems , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[4] Axel Jantsch,et al. Operating system sensitive device driver synthesis from implementation independent protocol specification , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).
[5] Keshab K. Parhi,et al. Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[6] Catherine H. Gebotys,et al. A minimum-cost circulation approach to DSP address-code generation , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[7] Kurt Keutzer,et al. Code density optimization for embedded DSP processors using data compression techniques , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[8] G. Borriello,et al. Communication synthesis for distributed embedded systems , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).
[9] Nikil D. Dutt,et al. Low-power memory mapping through reducing address bus activity , 1999, IEEE Trans. Very Large Scale Integr. Syst..
[10] Nikil D. Dutt,et al. Memory aware compilation through accurate timing extraction , 2000, Proceedings 37th Design Automation Conference.
[11] Marios C. Papaefthymiou,et al. Efficient Block Scheduling to Minimize Context Switching Time for Programmable Embedded Processors , 1999, Des. Autom. Embed. Syst..
[12] Srinivas Devadas,et al. Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[13] Rainer Leupers,et al. Exploiting conditional instructions in code generation for embedded VLIW processors , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).
[14] Luciano Lavagno,et al. Synthesis of software programs for embedded control applications , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[15] Jan M. Rabaey,et al. Predicting performance potential of modern DSPs , 2000, Proceedings 37th Design Automation Conference.
[16] Edwin A. Harcourt,et al. Generation of software tools from processor descriptions for hardware/software codesign , 1997, DAC.
[17] Catherine H. Gebotys. DSP address optimization using a minimum cost circulation technique , 1997, ICCAD 1997.
[18] Manfred Glesner,et al. Generation of interconnect topologies for communication synthesis , 1998, Proceedings Design, Automation and Test in Europe.
[19] Srinivas Devadas,et al. Application-specific memory management for embedded systems using software-controlled caches , 2000, Proceedings 37th Design Automation Conference.
[20] Srinivas Devadas,et al. Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures , 1999, Des. Autom. Embed. Syst..
[21] Luciano Lavagno,et al. Don't care-based BDD minimization for embedded software , 1998, DAC.
[22] Wayne H. Wolf,et al. SAMC: a code compression algorithm for embedded processors , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[23] Chantal Ykman-Couvreur,et al. Memory management for embedded network applications , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[24] Luca Benini,et al. Synthesis of low-overhead interfaces for power-efficient communication over wide buses , 1999, DAC '99.
[25] Hiroyuki Tomiyama,et al. Memory-CPU size optimization for embedded system designs , 1997, DAC.
[26] Sharad Malik,et al. Power analysis and minimization techniques for embedded DSP software , 1997, IEEE Trans. Very Large Scale Integr. Syst..
[27] William H. Mangione-Smith,et al. Function unit specialization through code analysis , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).
[28] Miodrag Potkonjak,et al. Application-driven synthesis of memory-intensive systems-on-chip , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[29] Mahmut T. Kandemir,et al. Influence of compiler optimizations on system power , 2000, Proceedings 37th Design Automation Conference.
[30] Diederik Verkest,et al. Combining software synthesis and hardware/software interface generation to meet hard real-time constraints , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).
[31] Bill Lin,et al. Efficient compilation of process-based concurrent programs without run-time scheduling , 1998, Proceedings Design, Automation and Test in Europe.
[32] Luca Benini,et al. Synthesis of application-specific memories for power optimization in embedded systems , 2000, Proceedings 37th Design Automation Conference.
[33] Joseph A. Fisher. Customized instruction-sets for embedded processors , 1999, DAC '99.
[34] Jan Madsen,et al. Integrating communication protocol selection with hardware/software codesign , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..