A PLL with ultra low phase noise for millimeter wave applications

An ultra low noise phase locked loop (PLL) for millimeter wave applications is presented. The complete design includes a mixer type phase detector, a divide-by-32 frequency divider, a VCO and an off-chip active low pass filter. A method for the phase noise optimization of the PLL is described. The chip was designed using a 0.8 µm SiGe HBT technology. The frequency can be tuned from 29.9 GHz to 33.1 GHz. The output phase noise is around −112 dBc/Hz at 1 MHz offset.

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