论文信息 - A highly latchup-immune 1 µm CMOS technology fabricated with 1 MeV ion implantation and self-aligned TiSi2

A highly latchup-immune 1 µm CMOS technology fabricated with 1 MeV ion implantation and self-aligned TiSi2

A 1 µm n-well CMOS technology with high latchup immunity is designed, realized, and characterized. The main features of this technology are : 1 MeV ion-implanted retrograde n-well, buried contact, arsenic-phosphorous double diffused n+/n-junction, self-aligned TiSi2on gate and diffusions with nitride spacer, and thin p epi on p+substrate. This technology has been demonstrated via the successful fabrication of high-performance 64K CMOS SRAM chips. It is also observed that the silicide plays an important role in latchup prevention since it reduces the emitter efficiencies of parasitic bipolar devices.

[1] Donald B. Estreich. The physics and modeling of latch-up and CMOS integrated circuits , 1980 .

[2] L.M. Terman,et al. A self-aligned 1-µm-channel CMOS technology with retrograde n-well and thin epitaxy , 1985, IEEE Transactions on Electron Devices.

[3] M. A. Shibib,et al. An analytic model for minority-carrier transport in heavily doped regions of silicon devices , 1981, IEEE Transactions on Electron Devices.

[4] Y. Nakagome,et al. An As-P(n+-n-)double diffused drain MOSFET for VLSI's , 1983, IEEE Transactions on Electron Devices.