Novel loop output buffer architecture and scheduling for efficient contention resolution in optical packet switching

A new loop output buffer architecture for optical packet switching is proposed. It is consisted of multiplex FDL loops, which are divided into k stages by k (M+1) x (M+1) switches. Using this architecture, a few FDL loops can provide large optical memories and get good packet-loss performance, and the delay performance can be improved by adding switches and buffer scheduling.