Parameterized block-based statistical timing analysis with non-Gaussian parameters, nonlinear delay functions

Variability of process parameters makes prediction of digital circuit timing characteristics an important and challenging problem in modern chip design. Recently, statistical static timing analysis (statistical STA) has been proposed as a solution. Unfortunately, the existing approaches either do not consider explicit gate delay dependence on process parameters (Liou, et al., 2001), (Orshansky, et al., 2002), (Devgan, et al., 2003), (Agarwal, et al., 2003) or restrict analysis to linear Gaussian parameters only (Visweswariah, et al., 2004), (Chang, et al., 2003). Here the authors extended the capabilities of parameterized block-based statistical STA (Visweswariah, et al., 2004) to handle nonlinear function of delays and non-Gaussian parameters, while retaining maximum efficiency of processing linear Gaussian parameters. The novel technique improves accuracy in predicting circuit timing characteristics and retains such benefits of parameterized block-based statistical STA as an incremental mode of operation, computation of criticality probabilities and sensitivities to process parameter variations. The authors' technique was implemented in an industrial statistical timing analysis tool. The experiments with large digital blocks showed both efficiency and accuracy of the proposed technique.