Current Mirror Array: A Novel Circuit Topology for Combining Physical Unclonable Function and Machine Learning

Edge analytics support industrial Internet of Things by pushing some data processing capacity to the edge of the network instead of sending the streaming data captured by the sensor nodes directly to the cloud. It is advantageous to endow machine learners for data reduction with suitable security primitives for privacy protection in edge computing devices to conserve area and power consumption. In this paper, we propose a novel physical unclonable function (PUF) based on current mirror array (CMA) circuits that reuses the circuit implementation of a machine learner–the extreme learning machine (ELM), which is a randomized neural network. Seven different challenge activation and response readout schemes are proposed to realize different weak and strong PUF functions from within the same CMA array. ELM endowed with such reconfigurable challenge-response mechanism is more robust and adaptable to different authentication protocols and security functions. Measurement results on <inline-formula> <tex-math notation="LaTeX">$0.35\mu m$ </tex-math></inline-formula> test chips demonstrate that the proposed strong PUF outperforms other state-of-the-art designs with smaller area/bit of <inline-formula> <tex-math notation="LaTeX">$9\times 10^{-36} \mu m^{2}$ </tex-math></inline-formula> and lower native bit error rate (BER) of 0.16% with an added overhead of less than 2.5% power and 2.9% area over the native ELM implementation.

[1]  Chip-Hong Chang,et al.  Design and Implementation of High-Quality Physical Unclonable Functions for Hardware-Oriented Cryptography , 2016 .

[2]  Daniel E. Holcomb,et al.  Initial SRAM State as a Fingerprint and Source of True Random Numbers for RFID Tags , 2007 .

[3]  Hongming Zhou,et al.  Extreme Learning Machine for Regression and Multiclass Classification , 2012, IEEE Transactions on Systems, Man, and Cybernetics, Part B (Cybernetics).

[4]  Srinivas Devadas,et al.  PUF Modeling Attacks on Simulated and Silicon Data , 2013, IEEE Transactions on Information Forensics and Security.

[5]  Y. Anzai,et al.  Pattern Recognition & Machine Learning , 2016 .

[6]  Ying Su,et al.  A Digital 1.6 pJ/bit Chip Identification Circuit Using Process Variations , 2008, IEEE Journal of Solid-State Circuits.

[7]  Himanshu Kaul,et al.  16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[8]  Massimo Alioto,et al.  14.3 15fJ/b static physically unclonable functions for secure chip identification with <2% native bit instability and 140× Inter/Intra PUF hamming distance separation in 65nm , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[9]  Giuseppe Iannaccone,et al.  CMOS Silicon Physical Unclonable Functions Based on Intrinsic Process Variability , 2011, IEEE Journal of Solid-State Circuits.

[10]  Mingoo Seok,et al.  Ultra-Compact and Robust Physically Unclonable Function Based on Voltage-Compensated Proportional-to-Absolute-Temperature Voltage Generators , 2016, IEEE Journal of Solid-State Circuits.

[11]  Patrick F. Dunn,et al.  Measurement and Data Analysis for Engineering and Science , 2017 .

[12]  K. Prasanthi,et al.  A 128-Channel Extreme Learning Machine-Based Neural Decoder for Brain Machine Interfaces , 2018 .

[13]  G. Edward Suh,et al.  Aegis: A Single-Chip Secure Processor , 2007, IEEE Des. Test Comput..

[14]  Srinivas Devadas,et al.  Modeling attacks on physical unclonable functions , 2010, CCS '10.

[15]  Sarmad Ullah Khan,et al.  Future Internet: The Internet of Things Architecture, Possible Applications and Key Challenges , 2012, 2012 10th International Conference on Frontiers of Information Technology.

[16]  Chong Kuan Chen,et al.  IoT Security: Ongoing Challenges and Research Opportunities , 2014, 2014 IEEE 7th International Conference on Service-Oriented Computing and Applications.

[17]  Arindam Basu,et al.  VLSI Extreme Learning Machine: A Design Space Exploration , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[18]  Marten van Dijk,et al.  A technique to build a secret key in integrated circuits for identification and authentication applications , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[19]  David Blaauw,et al.  14.2 A physically unclonable function with BER <10−8 for robust chip authentication using oscillator collapse in 40nm CMOS , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[20]  Georg Sigl,et al.  Side-Channel Analysis of PUFs and Fuzzy Extractors , 2011, TRUST.

[21]  David Blaauw,et al.  14.7 A 288µW programmable deep-learning processor with 270KB on-chip weight storage using non-uniform memory hierarchy for mobile intelligence , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

[22]  Wayne P. Burleson,et al.  On design of a highly secure PUF based on non-linear current mirrors , 2014, 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

[23]  G. Edward Suh,et al.  Physical Unclonable Functions for Device Authentication and Secret Key Generation , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[24]  Ingrid Verbauwhede,et al.  Low-Overhead Implementation of a Soft Decision Helper Data Algorithm for SRAM PUFs , 2009, CHES.

[25]  Chip-Hong Chang,et al.  A Low-Power Hybrid RO PUF With Improved Thermal Stability for Lightweight Applications , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[26]  Patrick Schaumont,et al.  A Robust Physical Unclonable Function With Enhanced Challenge-Response Set , 2012, IEEE Transactions on Information Forensics and Security.

[27]  Gu-Yeon Wei,et al.  14.3 A 28nm SoC with a 1.2GHz 568nJ/prediction sparse deep-neural-network engine with >0.1 timing error rate tolerance for IoT applications , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

[28]  Chip-Hong Chang,et al.  CMOS Image Sensor Based Physical Unclonable Function for Coherent Sensor-Level Authentication , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[29]  Srinivas Devadas,et al.  Controlled physical random functions , 2002, 18th Annual Computer Security Applications Conference, 2002. Proceedings..

[30]  Ulrich Rührmair,et al.  Combined Modeling and Side Channel Attacks on Strong PUFs , 2013, IACR Cryptol. ePrint Arch..

[31]  David Blaauw,et al.  2 A Physically Unclonable Function with BER < 10-8 for Robust Chip Authentication Using Oscillator Collapse in 40 nm CMOS , 2018 .

[32]  Jean-Pierre Seifert,et al.  Physical vulnerabilities of Physically Unclonable Functions , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[33]  Chee Kheong Siew,et al.  Extreme learning machine: Theory and applications , 2006, Neurocomputing.

[34]  Ulrich Rührmair,et al.  The Bistable Ring PUF: A new architecture for strong Physical Unclonable Functions , 2011, 2011 IEEE International Symposium on Hardware-Oriented Security and Trust.

[35]  Thomas Bäck,et al.  Evolutionary algorithms in theory and practice - evolution strategies, evolutionary programming, genetic algorithms , 1996 .

[36]  Elaine B. Barker,et al.  A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications , 2000 .

[37]  Chip-Hong Chang,et al.  A Retrospective and a Look Forward: Fifteen Years of Physical Unclonable Function Advancement , 2017, IEEE Circuits and Systems Magazine.

[38]  Chip-Hong Chang,et al.  Current mirror array: A novel lightweight strong PUF topology with enhanced reliability , 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

[39]  Jean-Pierre Seifert,et al.  Cloning Physically Unclonable Functions , 2013, 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).