Single-Event Transient Measurements in nMOS and pMOS Transistors in a 65-nm Bulk CMOS Technology at Elevated Temperatures
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[1] P. Eaton,et al. Single-Event Transient Pulse Quenching in Advanced CMOS Logic Circuits , 2009, IEEE Transactions on Nuclear Science.
[2] Chen Shuming,et al. Temperature Dependence of Digital SET Pulse Width in Bulk and SOI Technologies , 2008, IEEE Transactions on Nuclear Science.
[3] B. Narasimham,et al. Temperature Dependence of Digital Single-Event Transients in Bulk and Fully-Depleted SOI Technologies , 2009, IEEE Transactions on Nuclear Science.
[4] B.L. Bhuva,et al. Design Techniques to Reduce SET Pulse Widths in Deep-Submicron Combinational Logic , 2007, IEEE Transactions on Nuclear Science.
[5] T. Ohshima,et al. LET Dependence of Single Event Transient Pulse-Widths in SOI Logic Cell , 2009, IEEE Transactions on Nuclear Science.
[6] B L Bhuva,et al. Independent Measurement of SET Pulse Widths From N-Hits and P-Hits in 65-nm CMOS , 2010, IEEE Transactions on Nuclear Science.
[7] B. Narasimham,et al. Generation and Propagation of Single Event Transients in 0.18-$\mu{\rm m}$ Fully Depleted SOI , 2008, IEEE Transactions on Nuclear Science.
[8] A.F. Witulski,et al. Analysis of Parasitic PNP Bipolar Transistor Mitigation Using Well Contacts in 130 nm and 90 nm CMOS Technology , 2007, IEEE Transactions on Nuclear Science.
[9] B L Bhuva,et al. The Effect of Layout Topology on Single-Event Transient Pulse Quenching in a 65 nm Bulk CMOS Process , 2010, IEEE Transactions on Nuclear Science.
[10] L. W. Massengill,et al. Single event transient pulse width measurements in a 65-nm bulk CMOS technology at elevated temperatures , 2010, 2010 IEEE International Reliability Physics Symposium.
[11] M. Weybright,et al. High performance and low power transistors integrated in 65nm bulk CMOS technology , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
[12] peixiong zhao,et al. The effect of elevated temperature on digital single event transient pulse widths in a bulk CMOS technology , 2009, 2009 IEEE International Reliability Physics Symposium.
[13] B.L. Bhuva,et al. Laser Verification of Charge Sharing in a 90 nm Bulk CMOS Process , 2009, IEEE Transactions on Nuclear Science.
[14] B. Narasimham,et al. Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies , 2007, IEEE Transactions on Nuclear Science.
[15] B. Narasimham,et al. On-Chip Characterization of Single-Event Transient Pulsewidths , 2006, IEEE Transactions on Device and Materials Reliability.