A Packet Classifier Using a Parallel Branching Program Machine

A branching program machine (BM) is a special purpose processor that uses only two kinds of instructions: Branch and output instructions. Thus, the architecture for the BM is much simpler than that for a general purpose processor (MPU). Since the BM uses the dedicated instructions for a special purpose application, it is faster than the MPU. This paper presents a packet classifier using a parallel branching program machine (PBM). To reduce computation time and code size, first, a set of rules for the packet classifier is partitioned into groups. Then, they are evaluated by the PBM in parallel. Also, this paper shows a method to estimate the number of necessary BMs to realize the packet classifier. The PBM32 consisting of 32 BMs has been implemented on an FPGA, and compared with the Intel's Core2Duo@1.2GHz. The PBM32 is 8.1-11.1 times faster than the Core2Duo, and the PBM32 requires only 0.2-10.3 percent of the memory for the Core2Duo.

[1]  Ehab Al-Shaer,et al.  Analysis of Firewall Policy Rules Using Data Mining Techniques , 2006, 2006 IEEE/IFIP Network Operations and Management Symposium NOMS 2006.

[2]  Raymond T. Boute,et al.  The binary decision machine as programmable controller , 1976 .

[3]  Jonathan S. Turner,et al.  ClassBench: A Packet Classification Benchmark , 2005, IEEE/ACM Transactions on Networking.

[4]  Tsutomu Sasao,et al.  Implementation of multiple-output functions using PQMDDs , 2000, Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000).

[5]  Nakahara Hiroki,et al.  Emulation of Sequential Circuits by a Parallel Branching Program Machine , 2009 .

[6]  T. Sasao,et al.  Realization of sequential circuits by look-up table rings , 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..

[7]  Tsutomu Sasao,et al.  Implementation of Multiple-Valued CAM Functions by LUT Cascades , 2006, 36th International Symposium on Multiple-Valued Logic (ISMVL'06).

[8]  Paul J. Zsombor-Murray,et al.  Binary- Decision -Based Programmable Controllers Part I , 1983 .

[9]  Shinobu Nagayama,et al.  On the Minimization of Longest Path Length for Decision Diagrams , 2004 .

[10]  Tiziano Villa,et al.  Multi-valued decision diagrams: theory and applications , 1998 .

[11]  Tsutomu Sasao,et al.  A Parallel Branching Program Machine for Emulation of Sequential Circuits , 2009, ARC.

[12]  Nick McKeown,et al.  Packet classification on multiple fields , 1999, SIGCOMM '99.

[13]  Tsutomu Sasao,et al.  A Quaternary Decision Diagram Machine and the Optimization of its Code , 2009, 2009 39th International Symposium on Multiple-Valued Logic.

[14]  David E. Taylor Survey and taxonomy of packet classification techniques , 2005, CSUR.

[15]  Paul J. Zsombor-Murray,et al.  Advances in binary decision based programmable controllers , 1988 .

[16]  Tsutomu Sasao,et al.  Application of LUT cascades to numerical function generators , 2004 .

[17]  Jonathan S. Turner,et al.  Packet classification using extended TCAMs , 2003, 11th IEEE International Conference on Network Protocols, 2003. Proceedings..

[18]  Tsutomu Sasao,et al.  A Comparison of Architectures for Various Decision Diagram Machines , 2010, 2010 40th IEEE International Symposium on Multiple-Valued Logic.

[19]  Shinobu Nagayama,et al.  On the optimization of heterogeneous MDDs , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Shinobu Nagayama,et al.  Area-Time Complexities of Multi-Valued Decision Diagrams , 2004 .

[21]  Tsutomu Sasao On the Complexity of Classification Functions , 2008, 38th International Symposium on Multiple Valued Logic (ismvl 2008).

[22]  Sofia Cassel,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 2012 .