A 10 Gb/s 4-PAM transceiver with adaptive pre-emphasis

A 10 Gb/s 4-level pulse amplitude modulation (PAM) transceiver was implemented using a 0.13 μm CMOS process. The implemented 4-PAM transmitter employs current mode logics (CMLs) for high-speed operations. The proposed 4-PAM transceiver achieves a channel efficiency of 2 bit/symbol with adaptive pre-emphasis. The pre-emphasis was designed to be proportional to each 4-level's amplitude. The measured maximum data-rate was 10 Gb/s over 0.7-m cable and 3-cm printed circuit board (PCB) traces. The transmitter and receiver consume 245 mW and 69 mW, respectively. The measured bit-error rate (BER) was less than 10−12 at 10 Gb/s data rate.

[1]  Zhi-Ming Lin,et al.  Level selection based pre-emphasis for PAM transmitter , 2006 .

[2]  S.P. Voinigescu,et al.  A 60 mW per Lane, 4$,times,$23-Gb/s 2$ ^7 -$1 PRBS Generator , 2006, IEEE Journal of Solid-State Circuits.

[3]  D.A. Johns,et al.  A CMOS 10-gb/s power-efficient 4-PAM transmitter , 2004, IEEE Journal of Solid-State Circuits.

[4]  Tom Granberg,et al.  Handbook Of Digital Techniques For High-speed Design , 2004 .

[5]  Jinwook Burm,et al.  A 0.18 µm CMOS multi-Gb/s 10-PAM transmitter , 2009, Proceedings of the 2009 12th International Symposium on Integrated Circuits.

[6]  Sorin P. Voinigescu,et al.  A 60 mW per lane, 4 x 23-Gb/s 27-1 PRBS generator , 2006 .

[7]  T. Lee,et al.  A 0.4-/spl mu/m CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter , 1999 .

[8]  Michael P. Flynn,et al.  A low-power 8-PAM serial-transceiver in 0.5 μm digital CMOS , 2001 .

[9]  Jinwook Burm,et al.  A multi Gbps 10-PAM receiver in 0.18μm CMOS technology , 2009, Proceedings of the 2009 12th International Symposium on Integrated Circuits.