SON (silicon-on-nothing) technological CMOS platform: highly performant devices and SRAM cells

In this paper, we demonstrate for the first time full integration of highly performant NMOS and PMOS silicon-on-nothing (SON) devices into circuits. We demonstrated fully functional SRAMs cells with very good yield, showing static noise margin (SNM) of 175mV and write margin (WM, stable "read 0") above 500mV. The optimized SON devices show performance for NMOS and for PMOS that is among the best published data (with drive current up to 1100/350/spl mu/A//spl mu/m for 138/20nA//spl mu/m I/sub off/ for NMOS and PMOS devices respectively @V/sub dd/=1.2V, I/sub ox/=16A). Finally, we present also the implementation of the SON process into a new "localized SOI" architecture on bulk. This new and simplified SON process is also demonstrated by fully operational SRAM cells.