Power-aware signal integrity analysis of DDR4 data bus in onboard memory module

Designing data channels for the DDR4 memory is a challenging due to high data rates of 3.2GB/s per data signal at a low-voltage of 1.2V The coupling of simultaneous switching noise (SSN) in data signals in DDR4 memory modules is a critical signal and power integrity (SI/PI) problem. It is important to catch SI and PI problems at an early stage in design that requires fast and accurate power-aware signal integrity analysis. In this paper, power-aware signal integrity (PI-SI) analysis of data group signals of an onboard DDR4 memory module using power-aware IBIS model is presented. DDR4 power plane and data signals are analyzed using 3D Electromagnetic based PI-SI solver then the transient simulation is performed on combined PI data of power plane and data signals to get simultaneously switching noise (SSN) response of data bus and crosstalk between nearby channels.