An Area and Power Efficient Design of Single Edge Triggered D-Flip Flop

In this paper, a single edge-triggered, static D flip-flop design suitable, for low power and low area requirements is proposed. Advantageously, the flip-flop is realized using only ten transistors. The flip-flop is implemented using Master-Slave configuration and can be used for lower cost memory and microprocessor chips. The 0.6-micron technology is used to implement the design and the area and power results were compared with existing SET D FFs. Simulation results indicated that the circuit is capable of significant power savings.

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