Investigation of magnetic field attacks on commercial Magneto-Resistive Random Access Memory

In this work, we use a Field-Programmable Gate Array (FPGA) based memory testing setup to study the susceptibility of Magneto-Resistive Random Access Memory (MRAM) to interference by externally applied magnetic fields. We use a rare earth magnet field source to compare the transient and residual bit error response due to increasing magnetic field strengths and orientation during memory read, write and retention. Results indicate that the transient and residual error response in MRAM is proportional to applied field strength. Furthermore, MRAM displays resistance to disturbance during read interference and is more susceptible to destructive error during write-cycle magnetic interference.

[1]  Yuan-Jen Lee,et al.  Magnetic Memory: Contents , 2010 .

[2]  C. Efstathiou,et al.  A novel architecture to reduce test time in march-based SRAM tests , 2012, 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era.

[3]  Cheng-Wen Wu,et al.  Write Disturbance Modeling and Testing for MRAM , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  Cheng-Wen Wu,et al.  Test and Diagnosis Algorithm Generation and Evaluation for MRAM Write Disturbance Fault , 2008, 2008 17th Asian Test Symposium.

[5]  Mahmut T. Kandemir,et al.  Evaluating STT-RAM as an energy-efficient main memory alternative , 2013, 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

[6]  Bernard Dieny,et al.  Hybrid CMOS/Magnetic Memories (MRAMs) and Logic Circuits , 2014 .

[7]  E. Chen,et al.  Progress and Prospects of Spin Transfer Torque Random Access Memory , 2012, IEEE Transactions on Magnetics.

[8]  Ulf Schlichtmann,et al.  An Analysis of Industrial SRAM Test Results—A Comprehensive Study on Effectiveness and Classification of March Test Algorithms , 2014, IEEE Design & Test.

[9]  Bruce F. Cockburn,et al.  An optimal march test for locating faults in DRAMs , 1993, Records of the 1993 IEEE International Workshop on Memory Testing.

[10]  Swaroop Ghosh,et al.  Self-correcting STTRAM under magnetic field attacks , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[11]  Tom Zhong,et al.  A Study of Write Margin of Spin Torque Transfer Magnetic Random Access Memory Technology , 2010, IEEE Transactions on Magnetics.

[12]  Arnaud Virazel,et al.  Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling , 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

[13]  G. Tsiligiannis,et al.  Testing a Commercial MRAM Under Neutron and Alpha Radiation in Dynamic Mode , 2013, IEEE Transactions on Nuclear Science.

[14]  Cheng-Wen Wu,et al.  Diagnosis for MRAM write disturbance fault , 2007, 2007 IEEE International Test Conference.

[15]  J. Slaughter,et al.  A Fully Functional 64 Mb DDR3 ST-MRAM Built on 90 nm CMOS Technology , 2013, IEEE Transactions on Magnetics.

[16]  Swaroop Ghosh,et al.  Performance Impact of Magnetic and Thermal Attack on STTRAM and Low-Overhead Mitigation Techniques , 2016, ISLPED.

[17]  T. Watanabe,et al.  A novel U-shaped magnetic shield for perpendicular MRAM , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[18]  Mircea R. Stan,et al.  Advances and Future Prospects of Spin-Transfer Torque Random Access Memory , 2010, IEEE Transactions on Magnetics.

[19]  Denny D. Tang,et al.  Magnetic Memory: Fundamentals and Technology , 2010 .

[20]  Yuan-Jen Lee,et al.  Magnetic Memory by Denny D. Tang , 2010 .

[21]  C. Hafer,et al.  SEU, SET, and SEFI Test Results of a Hardened 16Mbit MRAM Device , 2012, 2012 IEEE Radiation Effects Data Workshop.

[22]  A. Alfred Kirubaraj,et al.  Model design of non-volatile SRAM based on Magnetic Tunnel Junction , 2009, 2009 2nd International Conference on Adaptive Science & Technology (ICAST).

[23]  Kaushik Roy,et al.  Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[24]  Janusz Nowak,et al.  Analytical MRAM test , 2014, 2014 International Test Conference.

[25]  T. Kasuya,et al.  A Theory of Metallic Ferro- and Antiferromagnetism on Zener's Model , 1956 .