The study of CD error in mid-local pattern area caused by develop loading effect

As the design rule has decreased in semiconductor manufacturing, the ITRS roadmap requires significantly tighter critical dimension control. Especially, CD error caused by develop loading become significant in the overall error budget and has approached to over 5nm. It is very difficult to control dissolution product making the change of dissolution rate by chemical flow direction in develop process. These days, the study of develop loading within global area has significantly progressed. However, we will focus on CD error in mid-local area by using a detailed analysis. And we evaluate these phenomenon caused by pattern density difference, called chemical flare. Even though using several developer types, CD error appears at the chip to chip boundary. It is impossible to correct CD error in this area by electron beam correction. Therefore, this paper analyzed about CD error in a value of several tens ~ hundreds nm. In view of develop loading, we will optimize develop process for improvement of CD error.