A vertex-list approach to 2D HW multitasking management in RTR FPGAs

This paper presents a novel approach to the management of run-time reconfigurable resources by an operating system with extended hardware multitasking functionality. Rectangular hardware tasks are placed at free locations in a two dimensional reconfigurable resource. Area management is done with techniques derived from bin-packing heuristics. A structure consisting of a set of vertex lists, each one describing the contour of each unoccupied area fragment in the reconfigurable device is presented. Some vertices of such structures may be used as candidate locations for the tasks, with bottomleft or top-right heuristics. We show that our approach has a reasonable complexity and gives better results, in terms of device fragmentation, than similar approaches.

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