Successful implementation of AES algorithm in hardware

Implementation of AES algorithm in hardware always found its bottleneck during the key scheduling process as it involves a lot of multiplication steps. This paper discusses how this bottleneck is identified, ways to overcome them and the implementation of the said algorithm with the improvement of the key scheduling result to a successful AES hardware implementation in Verilog Language. Efficiency is described using the clock speed it can manage after successful synthesis of the said AES verilog codes.