Cost-free scan: a low-overhead scan path design methodology

Conventional scan design imposes considerable area and delay overhead by using larger scan flip-flops and additional scan wires without utilizing the functionality of the combinational logic. We propose a novel low-overhead scan design methodology, called cost-free scan, which exploits the controllability of primary inputs to establish scan paths through the combinational logic. The methodology aims at reducing scan overhead by (1) analyzing the circuit to determine all the cost-free scan flip-flops, and (2) selecting the best primary input vector to establish the maximum number of cost-free scan flip-flops on the scan chain. Significant reduction in the scan overhead is achieved on ISCAS89 benchmarks, where in full scan environment, as many as 89% of the total flip-flops are found cost-free scannable, while in partial scan environment, reduction can be as high as 97% in scan flip-flops needed to break sequential loops.

[1]  R. Dandapani,et al.  Scan Design Using Standard Flip-Flops , 1987, IEEE Design & Test of Computers.

[2]  Janak H. Patel,et al.  An optimization based approach to the partial scan design problem , 1990, Proceedings. International Test Conference 1990.

[3]  James B. Angell,et al.  Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic , 1973, IEEE Transactions on Computers.

[4]  Chih-Chang Lin,et al.  Cost-free scan: a low-overhead scan path design methodology , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[5]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[6]  Robert K. Brayton,et al.  Sequential circuit design using synthesis and optimization , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[7]  F. C. Hennie.  Fault detecting experiments for sequential circuits , 1964, SWCT.

[8]  Sandip Kundu,et al.  On diagnosis of faults in a scan-chain , 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

[9]  Vishwani D. Agrawal,et al.  An architecture for synthesis of testable finite state machines , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[10]  Rabindra K. Roy,et al.  The Best Flip-Flops to Scan , 1991, 1991, Proceedings. International Test Conference.

[11]  S.M. Reddy,et al.  On determining scan flip-flops in partial-scan designs , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[12]  Vishwani D. Agrawal,et al.  Finite state machine synthesis with fault tolerant test function , 1992, DAC '92.

[13]  Randal E. Bryant,et al.  Efficient implementation of a BDD package , 1991, DAC '90.

[14]  Vishwani D. Agrawal,et al.  A partition and resynthesis approach to testable design of large circuits , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Melvin A. Breuer,et al.  The BALLAST Methodology for Structured Partial Scan Design , 1990, IEEE Trans. Computers.

[16]  Sharad Malik,et al.  Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications , 1994, 31st Design Automation Conference.

[17]  Janak H. Patel,et al.  A fault oriented partial scan design approach , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[18]  Alexander Miczo,et al.  Digital logic testing and simulation , 1986 .

[19]  Niraj K. Jha,et al.  Synthesis of sequential circuits for easy testability through performance-oriented parallel partial scan , 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

[20]  Henry Cox.  Synthesizing Circuits with Implicit Testability Constraints , 1995, IEEE Des. Test Comput..

[21]  K.-T. Cheng,et al.  A Partial Scan Method for Sequential Circuits with Feedback , 1990, IEEE Trans. Computers.

[22]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[23]  Thomas W. Williams,et al.  A logic design structure for LSI testability , 1977, DAC '77.

[24]  Niraj K. Jha,et al.  Synthesis of sequential circuits for parallel scan , 1992, [1992] Proceedings The European Conference on Design Automation.

[25]  V.D. Agrawal,et al.  Designing circuits with partial scan , 1988, IEEE Design & Test of Computers.

[26]  F. C. Hennine.  Fault detecting experiments for sequential circuits , 1964, SWCT 1964.

[27]  Vishwani D. Agrawal,et al.  An exact algorithm for selecting partial scan flip-flops , 1994, 31st Design Automation Conference.