Design of low-voltage wide tuning range CMOS multipass voltage-controlled ring oscillator
暂无分享,去创建一个
[1] Tad Kwasniewski,et al. CMOS VCO's for PLL frequency synthesis in GHz digital mobile radio communications , 1997 .
[2] Bishop Brock,et al. A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling , 2002, IEEE J. Solid State Circuits.
[3] Y. A. Eken. High frequency voltage controlled ring oscillators in standard CMOS , 2004 .
[4] Beomsup Kim,et al. Analysis of timing jitter in CMOS ring oscillators , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.
[5] G. Li Puma,et al. A 2-GHz low-phase-noise integrated LC-VCO set with flicker-noise upconversion minimization , 2000, IEEE Journal of Solid-State Circuits.
[6] M. Berroth,et al. The design of 5 GHz voltage controlled ring oscillator using source capacitively coupled current amplifier , 2003, IEEE MTT-S International Microwave Symposium Digest, 2003.
[7] A.M. Niknejad,et al. A 1.8-GHz LC VCO with 1.3-GHz tuning range and digital amplitude calibration , 2005, IEEE Journal of Solid-State Circuits.
[8] P. Hammer,et al. 2.4 GHz CMOS VCO with multiple tuning inputs , 2002 .
[9] Mohammed Ismail,et al. A 10-GHz CMOS quadrature LC-VCO for multirate optical applications , 2003 .
[10] Michael Ruegg,et al. A 2.5GHz phase-switching PLL using a supply controlled 2-delay-stage 10GHz ring oscillator for improved jitter/mismatch , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[12] Ali Hajimiri,et al. A general theory of phase noise in electrical oscillators , 1998 .
[13] M. Suzuki,et al. 3.2 GHz, 0.2 mu m gate CMOS 1/8 dynamic frequency divider , 1990 .
[14] M. Ismail,et al. CMOS PLL calibration techniques , 2004, IEEE Circuits and Devices Magazine.
[15] Thomas H. Lee,et al. The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES , 2003 .
[16] Y. A. Eken,et al. A 5.9-GHz Voltage-Controlled Ring Oscillator in 0.18- m CMOS , 2004 .
[17] Masanori Hashimoto,et al. A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process , 2004 .
[18] M. Thamsirianunt,et al. CMOS VCOs for PLL frequency synthesis in GHz digital mobile radio communications , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.
[19] A.A. Abidi,et al. Noise in RF-CMOS mixers: a simple physical model , 2000, IEEE Journal of Solid-State Circuits.
[20] Asad A. Abidi,et al. RF-CMOS oscillators with switched tuning , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).
[21] Carlo Samori,et al. Spectrum folding and phase noise in LC tuned oscillators , 1998 .
[22] Y. A. Eken,et al. A 5.9-GHz voltage-controlled ring oscillator in 0.18-/spl mu/m CMOS , 2004, IEEE Journal of Solid-State Circuits.
[23] R. Jacob Baker,et al. CMOS Circuit Design, Layout, and Simulation , 1997 .
[24] C.A.T. Salama,et al. Differential CMOS circuits for 622-MHz/933-MHz clock and data recovery applications , 2000, IEEE Journal of Solid-State Circuits.
[25] M. Berroth,et al. CMOS ring oscillator with quadrature outputs and 100 MHz to 3.5 GHz tuning range , 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).
[26] D. Leeson. A simple model of feedback oscillator noise spectrum , 1966 .
[27] Behzad Razavi,et al. Design of Analog CMOS Integrated Circuits , 1999 .
[28] Alan B. Grebene,et al. Analog Integrated Circuit Design , 1978 .
[29] Chih-Ming Hung,et al. An ultra low phase noise GSM local oscillator in a 0.09 /spl mu/m standard digital CMOS process with no high-Q inductors , 2004, 2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers.
[30] Beomsup Kim,et al. A low-noise, 900-MHz VCO in 0.6-/spl mu/m CMOS , 1999 .
[31] Salvatore Levantino,et al. Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion , 2002, IEEE J. Solid State Circuits.
[32] Ramesh Harjani,et al. Design of low-phase-noise CMOS ring oscillators , 2002 .
[33] Zhinian Shu,et al. A 2.4-GHz ring-oscillator-based CMOS frequency synthesizer with a fractional divider dual-PLL architecture , 2004, IEEE Journal of Solid-State Circuits.
[34] Kiat Seng Yeo,et al. RF CMOS low-phase-noise LC oscillator through memory reduction tail transistor , 2004, IEEE Trans. Circuits Syst. II Express Briefs.
[35] P. Wambacq,et al. Design-driven optimisation of a 90 nm RF CMOS process by use of elevated source/drain , 2003, ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003..
[36] Hoi-Jun Yoo,et al. A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique , 2003 .
[37] C. Sodini,et al. The impact of device type and sizing on phase noise mechanisms , 2005, IEEE J. Solid State Circuits.
[38] Wang Zhigong,et al. Design techniques of CMOS SCL circuits for Gb/s applications , 2001, ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549).
[39] David A. Johns,et al. Analog Integrated Circuit Design , 1996 .
[40] Michiel Steyaert,et al. A 1.8-GHz CMOS low-phase-noise voltage-controlled oscillator with prescaler , 1995, IEEE J. Solid State Circuits.
[41] Masanori Hashimoto,et al. A performance comparison of PLLs for clock generation using ring oscillator VCO and LC oscillator in a digital CMOS process , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).
[42] Yue Ping Zhang,et al. A Low-Noise Multi-GHz CMOS Multiloop Ring Oscillator With Coarse and Fine Frequency Tuning , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[43] Oscal T.-C. Chen,et al. A power-efficient wide-range phase-locked loop , 2002, IEEE J. Solid State Circuits.
[44] Wei-Bin Yang,et al. Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique , 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.
[45] Lizhong Sun,et al. A 1.25-GHz 0.35-μm monolithic CMOS PLL based on a multiphase ring oscillator , 2001, IEEE J. Solid State Circuits.
[46] HongMo Wang. A 1.8 V 3 mW 16.8 GHz frequency divider in 0.25 /spl mu/m CMOS , 2000 .
[47] Behzad Razavi,et al. A study of phase noise in CMOS oscillators , 1996, IEEE J. Solid State Circuits.
[48] C. Enz,et al. MOS transistor modeling for RF IC design , 2000, IEEE Journal of Solid-State Circuits.
[49] Chuan Yi Tang,et al. A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..
[50] M. Siccardi,et al. Power supply noise conversion to phase noise in CMOS frequency digital divider , 2002, Proceedings of the 2002 IEEE International Frequency Control Symposium and PDA Exhibition (Cat. No.02CH37234).