Reduced power dissipation through truncated multiplication

Reducing the power dissipation of parallel multipliers is important in the design of digital signal processing systems. In many of these systems, the products of parallel multipliers are rounded to avoid growth in word size. The power dissipation and area of rounded parallel multipliers can be significantly reduced by a technique known as truncated multiplication. With this technique, the least significant columns of the multiplication matrix are not used. Instead, the carries generated by these columns are estimated. This estimate is added with the most significant columns to produce the rounded product. This paper presents the design and implementation of parallel truncated multipliers. Simulations indicate that truncated parallel multipliers dissipate between 29 and 40 percent less power than standard parallel multipliers for operand sizes of 16 and 32 bits.

[1]  Earl E. Swartzlander,et al.  Power-delay characteristics of CMOS multipliers , 1997, Proceedings 13th IEEE Sympsoium on Computer Arithmetic.

[2]  M. Mehta,et al.  High-speed multiplier design using multi-input counter and compressor circuits , 1991, [1991] Proceedings 10th IEEE Symposium on Computer Arithmetic.

[3]  Ieee Circuits,et al.  Proceedings of the 39th Midwest Symposium on Circuits and Systems, August 18-21, 1996, Scheman Continuing Education Building, Iowa State Univeristy, Ames, Iowa , 1996 .

[4]  F.J. Taylor,et al.  Multiplier policies for digital signal processing , 1990, IEEE ASSP Magazine.

[5]  Y. C. Lim,et al.  Single-Precision Multiplier with Reduced Circuit Complexity for Signal Processing Applications , 1992, IEEE Trans. Computers.

[6]  Jun Iwamura,et al.  A high speed and low power CMOS/SOS multiplier-accumulator , 1983 .

[7]  Mohamed I. Elmasry,et al.  Circuit techniques for CMOS low-power high-performance multipliers , 1996 .

[8]  Andrew D. Booth,et al.  A SIGNED BINARY MULTIPLICATION TECHNIQUE , 1951 .

[9]  Earl E. Swartzlander,et al.  Parallel reduced area multipliers , 1995, J. VLSI Signal Process..

[10]  E. Swartzlander,et al.  Truncated multiplication with correction constant [for DSP] , 1993, Proceedings of IEEE Workshop on VLSI Signal Processing.

[11]  Rob A. Rutenbar,et al.  Exploring multiplier architecture and layout for low power , 1996, Proceedings of Custom Integrated Circuits Conference.

[12]  E. Swartzlander,et al.  Low power parallel multipliers , 1996, VLSI Signal Processing, IX.

[13]  Shyh-Jye Jou,et al.  A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design , 1995 .

[14]  Shen-Fu Hsiao,et al.  Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers , 1998 .

[15]  E. Abu-Shama,et al.  A fast and low power multiplier architecture , 1996, Proceedings of the 39th Midwest Symposium on Circuits and Systems.

[16]  Patrik Larsson,et al.  Low power multiplication for FIR filters , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

[17]  Gerald E. Sobelman,et al.  Low-power multiplier design using delayed evaluation , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[18]  G. De Micheli,et al.  Circuit and architecture trade-offs for high-speed multiplication , 1991 .

[19]  W Mclve.  a monolithic 16×16 digital multiplier , 1975 .

[20]  Earl E. Swartzlander.  Parallel Counters , 1973, IEEE Transactions on Computers.

[21]  Keshab K. Parhi,et al.  A theoretical approach to estimation of bounds on power consumption in digital multipliers , 1997 .

[22]  Edwin de Angel.  Low Power Digital Multipliers , 1997 .

[23]  Earl E. Swartzlander,et al.  Reduced area multipliers , 1993, Proceedings of International Conference on Application Specific Array Processors (ASAP '93).

[24]  Christopher S. Wallace,et al.  A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..

[25]  Stylianos D. Pezaris.  A 40-ns 17-Bit by 17-Bit Array Multiplier , 1971, IEEE Transactions on Computers.

[26]  Andreas Antoniou,et al.  Area-efficient multipliers for digital signal processing applications , 1996 .

[27]  Homayoon Sam,et al.  A Generalized Multibit Recoding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier Implementations , 1990, IEEE Trans. Computers.