Optimization of RF linearity in DG-MOSFETs

RF linearity of double-gate (DG) MOSFETs is investigated using accurate two-dimensional simulations. It is shown that the asymmetric DG-MOSFET is more linear than the symmetric counterpart and that DG-MOSFET linearity can be improved by a careful optimization of channel thickness, nonuniform doping profile and gate work function. For optimum linearity, a nonuniform doping profile and a thick (/spl sim/20 nm) silicon-on-insulator (SOI) layer is required. An intuitive description of this optimization is presented.

[1]  Meng-Hsueh Chiang,et al.  Speed superiority of scaled double-gate CMOS , 2002 .

[2]  Device linearity improvement by Al/sub 0.3/Ga/sub 0.7/As/In/sub 0.2/Ga/sub 0.8/As heterostructure doped-channel FETs , 1995 .

[3]  Keunwoo Kim,et al.  Double-gate CMOS: symmetrical- versus asymmetrical-gate devices , 2001 .

[4]  Behzad Razavi,et al.  RF Microelectronics , 1997 .

[5]  Bumman Kim,et al.  Linearity analysis of CMOS for RF application , 2002, 2002 IEEE MTT-S International Microwave Symposium Digest (Cat. No.02CH37278).

[6]  A. Asenov,et al.  Scaling of RF linearity in DG and SOI MOSFETs , 2003, The 11th IEEE International Symposium on Electron Devices for Microwave and Optoelectronic Applications, 2003. EDMO 2003..

[7]  P.W.H. de Vreede,et al.  RF-CMOS Performance Trends , 2000, 30th European Solid-State Device Research Conference.