Strategies to Ensure Electromigration Reliability of Cu/Low-k Interconnects at 10 nm

A key element for future silicon IC technology development is the containment of electromigration – induced failure of Cu / low-k interconnects. Continued progress in meeting electromigration reliability requirements for future technology nodes will require a multi-faceted approach to the problem: first the development of effective process solutions to limit the impact of technology scaling on electromigration life-time reduction; and second, the provision of models of failure that are representative of circuit operation to determine realistic current-limiting design rules. We will show that process solutions involve limiting the rate of transport along interfaces and grain boundaries in the damascene trench architecture using metal capping layers and Cu alloys. Most models of electromigration failure have been developed using DC stress conditions, while circuits predominantly operate with non-DC (pulsed DC or AC) signals. Understanding the relationship between failure under DC and non-DC conditions is a necessary aspect of realistic reliability characterization. In this paper we review: our recent studies that establish the relationship between Cu microstructure, metallic capping and dilute Cu alloy additions and thereby identify effective scenarios for mitigation with technology scaling; and experimental studies of electromigration failure under non-DC stress that explore the physical mechanisms involved. © The Author(s) 2014. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution Non-Commercial No Derivatives 4.0 License (CC BY-NC-ND, http://creativecommons.org/licenses/by-nc-nd/4.0/), which permits non-commercial reuse, distribution, and reproduction in any medium, provided the original work is not changed in any way and is properly cited. For permission for commercial reuse, please email: oa@electrochem.org. [DOI: 10.1149/2.0171501jss] All rights reserved.