Reducing cache leakage energy for hybrid SPM-cache architectures

In this paper, we study how to reduce the cache leakage energy efficiently in a hybrid SPM (Scratch-Pad Memory) and cache architecture. Since SPM can reduce the access frequency to the cache, we find it is possible to place the cache lines of the hybrid SPM-cache into the low power mode more aggressively than traditional leakage management for regular caches, which can reduce more leakage energy without significant performance degradation. Also, we propose a Hybrid Drowsy-Gated Vdd (HDG) technique, which can adaptively exploit both short and long idle intervals to minimize leakage energy with insignificant performance overhead.

[1]  Wei Zhang,et al.  Compiler-directed instruction cache leakage optimization , 2002, MICRO.

[2]  Wei Zhang,et al.  Compiler-based approach to reducing leakage energy of instruction scratch-pad memories , 2013, 2013 IEEE 31st International Conference on Computer Design (ICCD).

[3]  Kevin Skadron,et al.  State-preserving vs. non-state-preserving leakage control in caches , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[4]  Trevor Mudge,et al.  Drowsy instruction caches. Leakage power reduction using dynamic voltage scaling and cache sub-bank prediction , 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..

[5]  David A. Wood,et al.  A model for estimating trace-sample miss ratios , 1991, SIGMETRICS '91.

[6]  Eric Rotenberg,et al.  Adaptive mode control: A static-power-efficient cache design , 2003, TECS.

[7]  Wei Zhang,et al.  Hybrid SPM-cache architectures to achieve high time predictability and performance , 2013, 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors.

[8]  Krste Asanovic,et al.  Dynamic fine-grain leakage reduction using leakage-biased bitlines , 2002, ISCA.

[9]  Jaehyuk Huh,et al.  Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture , 2003, ISCA '03.

[10]  Peter Marwedel,et al.  Cache-aware scratchpad allocation algorithm , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[11]  Kevin Skadron,et al.  Adaptive Cache Decay using Formal Feedback Control , 2002 .

[12]  Jason Cong,et al.  An energy-efficient adaptive hybrid cache , 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

[13]  Enrico Macii,et al.  Architectural Leakage Power Minimization of Scratchpad Memories by Application-Driven Subbanking , 2010, IEEE Transactions on Computers.

[14]  Wei Zhang,et al.  Compiler-directed instruction cache leakage optimization , 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..

[15]  Alexander G. Dean,et al.  Leveraging both Data Cache and Scratchpad Memory through Synergetic Data Allocation , 2012, 2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium.

[16]  Mahmut T. Kandemir,et al.  Leakage-aware SPM management , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

[17]  Yan Meng,et al.  On the limits of leakage power reduction in caches , 2005, 11th International Symposium on High-Performance Computer Architecture.

[18]  David Blaauw,et al.  Drowsy caches: simple techniques for reducing leakage power , 2002, ISCA.

[19]  David Blaauw,et al.  Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction , 2002, MICRO.

[20]  Nikil D. Dutt,et al.  Efficient utilization of scratch-pad memory in embedded processor applications , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[21]  Mahmut T. Kandemir,et al.  Compiler-guided leakage optimization for banked scratch-pad memories , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[22]  Margaret Martonosi,et al.  Cache decay: exploiting generational behavior to reduce cache leakage power , 2001, ISCA 2001.

[23]  Kaushik Roy,et al.  Reducing leakage in a high-performance deep-submicron instruction cache , 2001, IEEE Trans. Very Large Scale Integr. Syst..