A Brief Survey of Non-Residue Based Computational Error Correction

The idea of computational error correction has been around for over half a century. The motivation has largely been to mitigate unreliable devices, manufacturing defects or harsh environments, primarily as a mandatory measure to preserve reliability, or more recently, as a means to lower energy by allowing soft errors to occasionally creep. While residue codes have shown great promise for this purpose, there have been several orthogonal non-residue based techniques. In this article, we provide a high level outline of some of these non-residual approaches.

[1]  Michael Nicolaidis,et al.  Efficient implementations of self-checking multiply and divide arrays , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[2]  J. Neumann Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components , 1956 .

[3]  Harvey L. Garner Error Codes for Arithmetic Operations , 1966, IEEE Trans. Electron. Comput..

[4]  Michael Nicolaidis,et al.  Carry checking/parity prediction adders and ALUs , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[5]  R. W. Watson,et al.  Self-checked computation using residue arithmetic , 1966 .

[6]  Wenjing Rao,et al.  Towards fault tolerant parallel prefix adders in nanoelectronic systems , 2008, 2008 Design, Automation and Test in Europe.

[7]  Michael Nicolaidis,et al.  Design of fault-secure parity-prediction Booth multipliers , 1998, Proceedings Design, Automation and Test in Europe.

[8]  Barry W. Johnson,et al.  Efficient use of time and hardware redundancy for concurrent error detection in a 32-bit VLSI adder , 1988 .

[9]  J. Mathew,et al.  Multiple Bit Error Detection and Correction in GF Arithmetic Circuits , 2010, 2010 International Symposium on Electronic System Design.

[10]  Christof Fetzer,et al.  ANB- and ANBDmem-Encoding: Detecting Hardware Errors in Software , 2010, SAFECOMP.

[11]  Thomas M. Conte,et al.  Computationally-redundant energy-efficient processing for y'all (CREEPY) , 2016, 2016 IEEE International Conference on Rebooting Computing (ICRC).

[12]  Kaushik Roy,et al.  Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and its Application to Digital Signal Processing Systems , 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

[13]  D. V. Smirnov,et al.  A method of monitoring execution of arithmetic operations on computers in computerized monitoring and measuring systems , 2008 .

[14]  Parag K. Lala,et al.  A technique for modular design of self-checking carry-select adder , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[15]  David T. Brown Error Detecting and Correcting Binary Codes for Arithmetic Operations , 1960, IRE Trans. Electron. Comput..

[16]  Christof Fetzer,et al.  AN-Encoding Compiler: Building Safety-Critical Systems with Commodity Hardware , 2009, SAFECOMP.

[17]  Chao-Kai Liu,et al.  Error-Correcting-Codes in Computer Arithmetic , 1972 .

[18]  Michael Gössel,et al.  New Self-checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft Errors , 2005, 14th Asian Test Symposium (ATS'05).

[19]  John F. Wakerly,et al.  Error detecting codes, self-checking circuits and applications , 1978 .

[20]  W. W. Peterson On Checking an Adder , 1958, IBM J. Res. Dev..

[21]  James Tschanz,et al.  A Low Cost Scheme for Reducing Silent Data Corruption in Large Arithmetic Circuits , 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

[22]  Osnat Keren,et al.  Arbitrary Error Detection in Combinational Circuits by Using Partitioning , 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

[23]  M. Forshaw,et al.  Architectures for reliable computing with unreliable nanodevices , 2001, Proceedings of the 2001 1st IEEE Conference on Nanotechnology. IEEE-NANO 2001 (Cat. No.01EX516).

[24]  Shlomi Dolev,et al.  Preserving Hamming Distance in Arithmetic and Logical Operations , 2013, J. Electron. Test..

[25]  Kaushik Roy,et al.  A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking , 2008, 2008 Design, Automation and Test in Europe.

[26]  C. Fetzer,et al.  Hardware Failure Virtualization Via Software Encoded Processing , 2007, 2007 5th IEEE International Conference on Industrial Informatics.

[27]  P. Forin,et al.  VITAL CODED MICROPROCESSOR PRINCIPLES AND APPLICATION FOR VARIOUS TRANSIT SYSTEMS , 1990 .

[28]  Rajit Manohar,et al.  Fault tolerant asynchronous adder through dynamic self-reconfiguration , 2005, 2005 International Conference on Computer Design.

[29]  E. E. Swartzlander,et al.  Time redundant error correcting adders and multipliers , 1992, Proceedings 1992 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.

[30]  Minxuan Zhang,et al.  Cost effective soft error mitigation for parallel adders by exploiting inherent redundancy , 2010, 2010 IEEE International Conference on Integrated Circuit Design and Technology.

[31]  Seyed Ghassem Miremadi,et al.  An Asymmetric Checkpointing and Rollback Error Recovery Scheme for Embedded Processors , 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

[32]  Shuguang Feng,et al.  Cost-efficient soft error protection for embedded microprocessors , 2006, CASES '06.

[33]  Mojtaba Valinataj,et al.  Fault Tolerant Arithmetic Operations with Multiple Error Detection and Correction , 2007, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007).

[34]  Ramesh Karri,et al.  Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics , 2006, Eleventh IEEE European Test Symposium (ETS'06).