Defect aware test patterns
暂无分享,去创建一个
[1] I. Pomeranz,et al. On testing of interconnect open defects in combinational logic circuits with stems of large fanout , 2002, Proceedings. International Test Conference.
[2] Irith Pomeranz,et al. Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.
[3] Sreejit Chakravarty,et al. Experimental evaluation of scan tests for bridges , 2002, Proceedings. International Test Conference.
[4] Premachandran R. Menon,et al. A Practical Approach to Fault Simulation and Test Generation for Bridging Faults , 1985, IEEE Transactions on Computers.
[5] Enamul Amyeen,et al. Evaluation of the quality of N-detect scan ATPG patterns on a processor , 2004, 2004 International Conferce on Test.
[6] Steven D. Millman,et al. AN ACCURATE BRIDGING FAULT TEST PATTERN GENERATOR , 1991, 1991, Proceedings. International Test Conference.
[7] Minesh B. Amin,et al. X-tolerant compression and application of scan-atpg patterns in a bist architecture , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[8] Bernd Becker,et al. Automatic test pattern generation for resistive bridging faults , 2004, Proceedings. 2004 IEEE International Workshop on Current and Defect Based Testing (IEEE Cat. No.04EX1004).
[9] Siyad C. Ma,et al. A comparison of bridging fault simulation methods , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).
[10] Keith Baker,et al. Defect-based delay testing of resistive vias-contacts a critical evaluation , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).
[11] Janusz Rajski,et al. Impact of multiple-detect test patterns on product quality , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[12] Sreejit Chakravarty,et al. Fault models for speed failures caused by bridges and opens , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).
[13] Irith Pomeranz,et al. Stuck-at tuple-detection: a fault model based on stuck-at faults for improved defect coverage , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).
[14] R. D. Blanton,et al. Analyzing the effectiveness of multiple-detect test sets , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[15] Nilanjan Mukherjee,et al. Embedded deterministic test for low cost manufacturing test , 2002, Proceedings. International Test Conference.
[16] M. Ray Mercer,et al. Defect-Oriented Testing and Defective-Part-Level Prediction , 2001, IEEE Des. Test Comput..
[17] Haluk Konuk. Voltage- and current-based fault simulation for interconnect open defects , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[18] Robert C. Aitken,et al. Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholds , 1993, Proceedings of IEEE International Test Conference - (ITC).
[19] Sandip Kundu,et al. Defect-Based Test : A Key Enabler for Successful Migration to Structural Test , 1999 .
[20] M. Ray Mercer,et al. On efficiently and reliably achieving low defective part levels , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).
[21] Edward J. McCluskey,et al. An experimental chip to evaluate test techniques experiment results , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).
[22] Wojciech Maly,et al. CMOS bridging fault detection , 1990, Proceedings. International Test Conference 1990.