论文信息 - FPGA-Based Implementation of RAM with Asymmetric Port Widths for Run-Time Reconfiguration

FPGA-Based Implementation of RAM with Asymmetric Port Widths for Run-Time Reconfiguration

In this paper, we present a HDL description of a RAM with asymmetric port widths which allows read and write operations with different data size. This RAM is suitable for implementing run-time reconfigurable systems in FPGA The proposed RAM specification has been tested with different target devices.

Antonio Abad Civit Balcells | Ignacio Garcia-Vargas | Raouf Senhadji-Navarro | Gabriel Jiménez-Moreno

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