1.5-bit mismatch-insensitive MDAC with reduced input capacitive loading

A new mismatch insensitive 1.5-bit multiplying digital-analogue converter (MDAC) is proposed. This circuit samples the input in closed-loop form using the opamp in non-inverting configuration; hence, only the parasitic input capacitance loads the previous stage. This technique uses a fully-differential four-input OTA instead of two single-ended two-input OTAs to further improve power consumption and matching.

[1]  Manuel Medeiros Silva,et al.  Switched-Capacitor Multiply-By-Two Amplifier Insensitive to Component Mismatches , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  Izzet Kale,et al.  Multiply-by-two gain stage with reduced mismatch sensitivity , 2005 .

[3]  Patrick Quinn,et al.  Capacitor matching insensitive algorithmic ADC requiring no calibrations , 2003, Integr..

[4]  Franco Maloberti,et al.  SC amplifier and SC integrator with an accurate gain of 2 , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.

[5]  Omid Shoaei,et al.  A Novel Low Power 1 GS/s S&H Architecture With Improved Analog Bandwidth , 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.