ASIC design of MUL-RED Radix-2 Pipeline FFT circuit for 802.11ah system

In this paper, we propose a multiplier-reduction (MUL-RED) Radix-2 Pipeline FFT processor for 802.11ah IoT sensors. Utilizing the symmetry of Twiddle factors we show two ideas to reduce the hardware cost and power consumption. Firstly, the complex-multipliers in the last 4 layers are replaced by gain blocks. Secondly, in the remained layers we store only one fourth of the required Twiddle factors to reduce the ROM amount by 4 times. Based on the proposed architecture, we implement the 16-point FFT and 64-point FFT circuits in ASIC CMOS 0.18 μm technology. Area and dynamic power of the proposed 16-point FFT are respectively reduced by 28% and 10% as compared to those of the conventional Radix-2 Pipeline one. Whereas, the proposed 64-point FFT costs 0.34mm2 area and consumes 21.43 mW power at 50 MHz, which are much smaller than the other works. In addition, to find out the optimal number of fractional bit width of FFT's data flow, we conduct BER/PER simulation and show the results in the paper.