Scalable Adaptive Scan (SAS)
暂无分享,去创建一个
[1] Rohit Kapur,et al. Minimizing the Impact of Scan Compression , 2007, 25th IEEE VLSI Test Symposium (VTS'07).
[2] Kuen-Jong Lee,et al. Using a single input to support multiple scan chains , 1998, ICCAD '98.
[3] Erik Jan Marinissen,et al. Hierarchy-Aware and Area-Efficient Test Infrastructure Design for Core-Based System Chips , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[4] Haihua Yan,et al. Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction , 2007, 25th IEEE VLSI Test Symposium (VTS'07).
[5] Sudhakar M. Reddy,et al. Convolutional compaction of test responses , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[6] Vikram Iyengar,et al. A unified SOC test approach based on test data compression and TAM design , 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.
[7] Srivaths Ravi,et al. Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[8] Rohit Kapur,et al. A reconfigurable shared scan-in architecture , 2003, Proceedings. 21st VLSI Test Symposium, 2003..
[9] André Ivanov,et al. Time domain multiplexed TAM: implementation and comparison , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[10] Nur A. Touba,et al. Survey of Test Vector Compression Techniques , 2006, IEEE Design & Test of Computers.
[11] Bashir M. Al-Hashimi,et al. Compression considerations in test access mechanism design , 2005 .
[12] P ? ? ? ? ? ? ? % ? ? ? ? , 1991 .
[13] Sun Yihe,et al. A scalable test mechanism and its optimization for test access to embedded cores , 2001, ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549).
[14] Erik Jan Marinissen,et al. A structured and scalable mechanism for test access to embedded reusable cores , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[16] Rohit Kapur,et al. Evaluation of Entropy Driven Compression Bounds on Industrial Designs , 2008, 2008 17th Asian Test Symposium.
[17] Ming Zhang,et al. Hierarchical Test Compression for SoC Designs , 2008, IEEE Design & Test of Computers.
[18] Janak H. Patel,et al. An incremental algorithm for test generation in Illinois scan architecture based designs , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[19] Hideo Fujiwara,et al. System-on-chip test scheduling with reconfigurable core wrappers , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[20] Nur A. Touba,et al. Using Limited Dependence Sequential Expansion for Decompressing Test Vectors , 2006, 2006 IEEE International Test Conference.