Fast Generation of Statistically- ase Modeli~~ of On-Chip Interconnect

In this paper, we describe a novel methodology for obtaining statistically-based worst case (i.e. 3-0) R (resistance), C (capacitance), and delay given variations in interconnectrelated process parameters. Qur approach is based on a weighted root-sum square method to derive 3- G C. A Monte Carlo-based method is used for the generation of 3- R as well as randomized distributed RC nets to obtain realistic 3o delays for long interconne paths. Using this methodolog on a 0.35 pm process, CT delay estimation c corner worst case delay can b is described. An lity of this methodology.