The VLSI Architecture and Implementation of a Low Complexity and Highly Efficient Configurable SVD Processor for MIMO Communication Systems

This paper presents the design and implementation of a low complexity and highly efficient configurable singular value decomposition (SVD) processor for 2 × 2, 4 × 4, 6 × 6, and 8 × 8 MIMO wireless communication systems. In order to minimize the area complexity while maintaining comparable throughput, novel data-processing sequences are proposed so that costly matrix multipliers are eliminated. Furthermore, data dependencies are greatly mitigated due to the proposed processing sequences. Therefore, a highly optimized pipelined architecture is designed where the resource utilization and hardware efficiency are significantly improved. Moreover, circuit level optimizations are also applied to further enhance the performance of the proposed SVD processor. The proposed SVD architecture has been implemented with 90 nm technology at 500 MHz clock frequency. The post-layout estimations show that the proposed SVD processor achieves a throughput of 1.1 M matrices/s for 8 × 8 MIMO communication systems with the hardware complexity of 192.2 kilo Gate Equivalents. Compared to the state-of-the-art design that supports 2 × 2, 4 × 4, 6 × 6, and 8 × 8 MIMO configurations, the proposed architecture demonstrates a 46% reduction in area complexity and a 22% improvement in hardware efficiency.