FAST: FPGA-based Acceleration of Simulator Timing models

Computer architectures have long been sufficiently complex to require simulation to model performance with any precision. Building accurate simulators, however, is a time-consuming and error-prone task that can consume a large amount of engineering resources. In fact, the difficulty of building a new simulator whose results can be relied on is a significant barrier to entry for novel architectures that is probably influencing what architecture exploration is actually done; it is much easier to start with a working, verified simulator than brewing a new one from scratch. In addition, cycle-accurate simulators are invariably slow since they model parallel hardware structures that are inefficient to simulate in software. Current cycle-accurate simulators run at about 10K instructions per second, much too slow to run realistic applications and thus relegating such simulators to either run toy benchmarks or requiring sampling techniques to reduce the number of instructions that need to be run.