Anti-single event upset and anti-single event transient resettable scanning structure D trigger

The invention discloses an anti-single event upset and anti-single event transient resettable scanning structure D trigger, for the purpose of solving the problems of not high anti-single event upset capability and not high anti-single event transient capability of a conventional resettable scanning structure D trigger. The resettable scanning structure D trigger provided by the invention is composed of a buffer circuit, a scanning control buffer circuit, a reset buffer circuit, a clock circuit, a master latch register, a slave latch register and an output buffer circuit. The master latch register and the slave latch register are latch registers with redundancy reinforcement. The master latch register and the slave latch register are connected in series and are both connected with the clock circuit and the reset buffer circuit. The master latch register is also connected with the buffer circuit and the scanning control buffer circuit. The slave latch register is also connected with the output buffer circuit. According to the invention, mutually redundant C MOS circuits are separated from the master latch register and the slave latch register so that the anti-single event upset capability is improved. The buffer circuit enables no errors to be generated under a single event transient pulse which lasts for quite a long time. A dual-mode redundancy pathway further enhances the anti-single event upset capability.