暂无分享,去创建一个
[1] Marco Chiappetta,et al. Real time detection of cache-based side-channel attacks using hardware performance counters , 2016, Appl. Soft Comput..
[2] Yutao Liu,et al. Transparent and Efficient CFI Enforcement with Intel Processor Trace , 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).
[3] Francisco J. Cazorla,et al. Cache Side-Channel Attacks and Time-Predictability in High-Performance Critical Real-Time Systems , 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).
[4] Danfeng Zhang,et al. Identifying Cache-Based Side Channels through Secret-Augmented Abstract Interpretation , 2019, USENIX Security Symposium.
[5] Adi Shamir,et al. Efficient Cache Attacks on AES, and Countermeasures , 2010, Journal of Cryptology.
[6] Michael K. Reiter,et al. Düppel: retrofitting commodity operating systems to mitigate cache side channels in the cloud , 2013, CCS.
[7] Ravi Iyer,et al. Cache QoS: From concept to reality in the Intel® Xeon® processor E5-2600 v3 product family , 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).
[8] Cemal Yilmaz,et al. SpyDetector: An approach for detecting side-channel attacks at runtime , 2018, International Journal of Information Security.
[9] Moinuddin K. Qureshi. New Attacks and Defense for Encrypted-Address Cache , 2019, 2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA).
[10] Stefan Mangard,et al. Cache Template Attacks: Automating Attacks on Inclusive Last-Level Caches , 2015, USENIX Security Symposium.
[11] Gaël Varoquaux,et al. Scikit-learn: Machine Learning in Python , 2011, J. Mach. Learn. Res..
[12] Hovav Shacham,et al. The geometry of innocent flesh on the bone: return-into-libc without function calls (on the x86) , 2007, CCS '07.
[13] Michael Hamburg,et al. Spectre Attacks: Exploiting Speculative Execution , 2018, 2019 IEEE Symposium on Security and Privacy (SP).
[14] Ruby B. Lee,et al. New cache designs for thwarting software cache-based side channel attacks , 2007, ISCA '07.
[15] Vitaly Shmatikov,et al. Memento: Learning Secrets from Process Footprints , 2012, 2012 IEEE Symposium on Security and Privacy.
[16] Zhenkai Liang,et al. Jump-oriented programming: a new class of code-reuse attack , 2011, ASIACCS '11.
[17] Michael K. Reiter,et al. A Software Approach to Defeating Side Channels in Last-Level Caches , 2016, CCS.
[18] Hao Wu,et al. Newcache: Secure Cache Architecture Thwarting Cache Side-Channel Attacks , 2016, IEEE Micro.
[19] Chris Fallin,et al. Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors , 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).
[20] Yuval Yarom,et al. FLUSH+RELOAD: A High Resolution, Low Noise, L3 Cache Side-Channel Attack , 2014, USENIX Security Symposium.
[21] Xiao Liu,et al. CacheD: Identifying Cache-Based Timing Channels in Production Software , 2017, USENIX Security Symposium.
[22] Ruby B. Lee,et al. CloudRadar: A Real-Time Side-Channel Attack Detection System in Clouds , 2016, RAID.
[23] Gernot Heiser,et al. CATalyst: Defeating last-level cache side channel attacks in cloud computing , 2016, 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA).
[24] Vikram S. Adve,et al. KCoFI: Complete Control-Flow Integrity for Commodity Operating System Kernels , 2014, 2014 IEEE Symposium on Security and Privacy.
[25] Michael M. Swift,et al. Scheduler-based Defenses against Cross-VM Side-channels , 2014, USENIX Security Symposium.
[26] Tao Zhang,et al. HIDE: an infrastructure for efficiently protecting information leakage on the address bus , 2004, ASPLOS XI.
[27] Michael Hamburg,et al. Meltdown: Reading Kernel Memory from User Space , 2018, USENIX Security Symposium.
[28] Josep Torrellas,et al. Secure hierarchy-aware cache replacement policy (SHARP): Defending against cache-based side channel attacks , 2017, 2017 ACM/IEEE 44th Annual International Symposium on Computer Architecture (ISCA).
[29] Nael B. Abu-Ghazaleh,et al. Non-monopolizable caches: Low-complexity mitigation of cache side channel attacks , 2012, TACO.
[30] David R. Kaeli,et al. Side-channel power analysis of a GPU AES implementation , 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).
[31] Gernot Heiser,et al. Last-Level Cache Side-Channel Attacks are Practical , 2015, 2015 IEEE Symposium on Security and Privacy.
[32] Nhien-An Le-Khac,et al. A Survey of Electromagnetic Side-Channel Attacks and Discussion on their Case-Progressing Potential for Digital Forensics , 2019, Digit. Investig..
[33] Meng Wu,et al. Eliminating timing side-channel leaks using program repair , 2018, ISSTA.
[34] Trent Jaeger,et al. GRIFFIN: Guarding Control Flows Using Intel Processor Trace , 2017, ASPLOS.
[35] Moinuddin K. Qureshi. CEASER: Mitigating Conflict-Based Cache Attacks via Encrypted-Address and Remapping , 2018, 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[36] Naomi Benger,et al. Recovering OpenSSL ECDSA Nonces Using the FLUSH+RELOAD Cache Side-channel Attack , 2014, IACR Cryptol. ePrint Arch..
[37] Simha Sethumadhavan,et al. TimeWarp: Rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacks , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).
[38] Serge J. Belongie,et al. SD-VBS: The San Diego Vision Benchmark Suite , 2009, 2009 IEEE International Symposium on Workload Characterization (IISWC).
[39] Martín Abadi,et al. Control-flow integrity , 2005, CCS '05.
[40] A. Adam Ding,et al. SCADET: A Side-Channel Attack Detection Tool for Tracking Prime-Probe , 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[41] Xuxian Jiang,et al. Mitigating code-reuse attacks with control-flow locking , 2011, ACSAC '11.
[42] William R. Harris,et al. Enforcing Unique Code Target Property for Control-Flow Integrity , 2018, CCS.
[43] Srinivas Devadas,et al. DAWG: A Defense Against Cache Timing Attacks in Speculative Execution Processors , 2018, 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[44] Taesoo Kim,et al. STEALTHMEM: System-Level Protection Against Cache-Based Side Channel Attacks in the Cloud , 2012, USENIX Security Symposium.
[45] Klaus Wagner,et al. Flush+Flush: A Fast and Stealthy Cache Attack , 2015, DIMVA.
[46] Adi Shamir,et al. Cache Attacks and Countermeasures: The Case of AES , 2006, CT-RSA.
[47] Adi Shamir,et al. RSA Key Extraction via Low-Bandwidth Acoustic Cryptanalysis , 2014, CRYPTO.
[48] Torsten Hoefler,et al. A fast analytical model of fully associative caches , 2019, PLDI.
[49] Thomas F. Wenisch,et al. Foreshadow: Extracting the Keys to the Intel SGX Kingdom with Transient Out-of-Order Execution , 2018, USENIX Security Symposium.
[50] Chao Zhang,et al. Practical Control Flow Integrity and Randomization for Binary Executables , 2013, 2013 IEEE Symposium on Security and Privacy.