Design and manufacturing process co-optimization in nano-technology

Newest manufacturing technologies with feature sizes smaller than 20nm and FinFET devices have favored more restrictive design rules for manufacturability while suffering from electrical limitations of electromigration (EM) and variability. Designers can no longer reap the benefits in power, performance and area by simply relying on feature size miniature with contemporary design techniques. This work illustrates the importance of design and manufacturing technology co-optimization. Limitations in lithography has led to slower reduction in metal and VIA shape spacing than critical dimensions, which prompts for co-optimization in metallization stack, power mesh planning, standard cell designs and placement algorithms. New routing algorithms and parasitics modeling are required to achieve improved design performance under sky-rocketing metal resistance especially at lower metal levels. Ever-lowering maximum current limits due to EM has prompted new approaches in placement optimization to counteract the potential explosion in EM violations. Adoption of FinFET has allowed ultra-low Vdd designs, which requires careful consideration of Vth offerings that allow proper trade-off between variability, area and power efficiency.