Analysis of STI Thin-SOI LDMOS transistors for Smart Power and high frequency applications

This paper is addressed to the study of 80V STILDMOS transistors in a Thin-SOI technology by means of 2D numerical simulations. Extensive 2D numerical simulation results allow to compare the electrical performance of the proposed novel STI LDMOS structure with that of a conventional LDMOS in terms of breakdown voltage, specific on-resistance, transconductance (gm), and cut-off frequency (fT). Moreover, the impact of the STI length (LSTI) and the N-drift implantation energy on the electrical characteristics are considered in detail. The benefits of applying the STI concept to higher voltage Thin-SOI LDMOS (in the range of 80V) is analysed in this paper.