Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design

On-chip interconnects exhibit clear frequency-dependence in both resistance and inductance. A compact ladder circuit model is developed to capture this behavior, and we examine its impact on digital and RF circuit design. It is demonstrated that the use of DC values for R and L is sufficient for delay analysis, but RL frequency dependence is critical for the analysis of signal integrity, shield line insertion, power supply stability, and RF inductor performance.

[1]  A. Taylor,et al.  An on-chip voltage regulator using switched decoupling capacitors , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[2]  Jamil Kawa,et al.  Modeling and analysis of differential signaling for minimizing inductive cross-talk , 2001, DAC '01.

[3]  Yu Cao,et al.  Frequency-independent equivalent circuit model for on-chip spiral inductors , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

[4]  Sharad Mehrotra,et al.  Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[5]  Yu Cao,et al.  RLC signal integrity analysis of high-speed global interconnects [CMOS] , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[6]  Gaofeng Wang,et al.  On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[7]  Yu Cao,et al.  New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[8]  J. Long,et al.  The modeling, characterization, and design of monolithic inductors for silicon RF IC's , 1997, IEEE J. Solid State Circuits.

[9]  裕幸 飯田,et al.  International Technology Roadmap for Semiconductors 2003の要求清浄度について - シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について - , 2004 .

[10]  D. P. Neikirk,et al.  Compact equivalent circuit model for the skin effect , 1996, 1996 IEEE MTT-S International Microwave Symposium Digest.

[11]  George Papadopoulos,et al.  Full-wave PEEC time-domain method for the modeling of on-chipinterconnects , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  John Lillis,et al.  Interconnect Analysis and Synthesis , 1999 .