A Boundary Element Method for Substrate Cross-talk Analysis

An increasingly urgent topic for the realization of densely packed (mixed signal) integrated circuits is prevention of cross-talk via the substrate. Due to decreasing distances between components and increasing operating frequencies, the coupling between components and/or circuit blocks becomes stronger and affects the circuit behaviour more and more. This paper proposes a Boundary Element Method for calculating an admittance matrix for the substrate in order to analyze the parasitic coupling during layout verification. Some issues for the implementation in a layout extraction package, Space [3, 4], will be discussed. Finally, the paper will present relevant examples and comparison with results from the literature.