Effect of reverse biased voltage at source and drain on plasma damage
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[1] W. Lukaszek,et al. Device effects and charging damage: correlations between SPIDER-MEM and CHARM/sup R/-2 , 1999, 1999 4th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.99TH8395).
[2] Durga Misra,et al. LETTER TO THE EDITOR: Effect of source and drain junctions on plasma charging , 1998 .
[3] Durga Misra,et al. Is NMOSFET Hot Carrier Lifetime Degraded By Charging Damage? , 1997, 2nd International Symposium on Plasma Process-Induced Damage.
[4] P. K. Aum,et al. Controlling plasma charge damage in advanced semiconductor manufacturing. Challenge of small feature size device, large chip size, and large wafer size , 1998 .
[5] T. Brożek. Annealing of plasma charging damage and residual degradation in MOS transistors , 1999, 1999 4th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.99TH8395).
[6] Chenming Hu,et al. TOPICAL REVIEW: Thin gate oxide damage due to plasma processing , 1996 .
[7] T. Wen,et al. InGaN/GaN tunnel-injection blue light-emitting diodes , 2002 .
[8] J. Stathis,et al. Ultra-thin oxide reliability for ULSI applications , 2000 .
[9] David E. Dyer,et al. Device Effects and Charging Damage : Correlations Between SPIDER-MEM and CHARM-2 , 1999 .
[10] K.P. Cheung. An efficient method for plasma-charging damage measurement , 1994, IEEE Electron Device Letters.
[11] Chih-Tang Sah,et al. Two pathways of positive oxide‐charge buildup during electron tunneling into silicon dioxide film , 1994 .