Design of a low power binary counter using bistable storage element

An architecture for a O(1)-loss irreversible n-bit counter is presented in this paper. It is presented as an initial stepping stone application that is suitable for clarifying the potential energy-efficiency advantages of reversible computing. It is based on using fairly standard, irreversible, semi-static CMOS logic. Care is taken to ensure that energy is not dissipated at subsequent counter bits, except those that are actually changing values on a given cycle. The design utilizes two-phase non-overlapping clocks, phi0 and phi1 with fast rise and fall times. For high system level energy-efficiency, the clocks were generated resonantly using the rotary clock scheme. XOR gates serve as phase detectors with AND gates helping to maintain parity checking. Transmission gates ensure a semi-static logic since the logic levels are restored only during the high portion of the clock period. We compared the power dissipation of an 8-bit counter designed using this logic to a standard 8-bit binary counter design using flip-flops in the 50 nm process and recorded a power advantage of about 60%. A prototype will be sent to MOSIS for fabrication to confirm energy advantage of this design after testing.