Secure transmission of gate level description

Modern system-on-chip (SoC) design cycle strongly depends on secure exchange of intellectual properties (IPs) between core-authors, integrators, foundries etc. However the sharing of IP between authorities involves high security risks in today's competitive market. Since IP usually involves large amount of data, conventional message encryption techniques needs improvised use in this case. In this paper we have proposed a technique for secure transmission of the gate level description of a combinational circuit over public network. An easy to implement and computationally inexpensive encryption technique is used to encrypt the description. It enables intended receiver to decrypt the description using owner's certificate. It also facilitates in identifying any intentional modification in the description made by any unauthorized party. Experimental results show that the proposed technique can withstand variety of attacks from intruders.

[1]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[2]  Antonio García,et al.  IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  I. Torunoglu,et al.  Watermarking-based copyright protection of sequential functions , 2000, IEEE Journal of Solid-State Circuits.

[4]  Chip-Hong Chang,et al.  Watermarking for IP Protection through Template Substitution at Logic Synthesis Level , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[5]  M. Potkonjak,et al.  Hierarchical watermarking for protection of DSP filter cores , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[6]  Gang Qu,et al.  Soft IP Protection: Watermarking HDL Codes , 2004, Information Hiding.

[7]  Jason Cong,et al.  Protecting Combinational Logic Synthesis Solutions , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Niraj K. Jha,et al.  Switching and Finite Automata Theory: Frontmatter , 2009 .

[9]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[10]  Edoardo Charbon.  Hierarchical watermarking in IC design , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[11]  Arlindo L. Oliveira.  Techniques for the creation of digital watermarks in sequentialcircuit designs , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Miodrag Potkonjak,et al.  Constraint-based watermarking techniques for design IP protection , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..