Low-cost and power-ecient thread collision detection scheme for shared caches in a real-time multithreaded embedded processor

This paper addresses an important issue in a real-time multithreaded embedded processor where several active hardware threads share the critical resources such as caches in the processor. Thread interferences or collisions could lead to severe performance degradations on the real-time threads. Although the cache interference issue on real- time multithreaded processors has been studied before, no cost-eective and simpler hardware solutions were proposed to maintain the single thread performance of the real-time thread while still letting the low-priority threads progress. A novel technique called collision tag is proposed to address these issues. Progressively, the collision tag scheme can be reduced into a more power-ecient form called collision bit vector, with almost no impact in the overall performance of