Process-design considerations for three dimensional memory integration
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T. Kirihata | S.S. Iyer | R. Malik | M.R. Wordeman | J. Barth | R.H. Hannon
[1] Richard E. Matick,et al. A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier , 2008, IEEE Journal of Solid-State Circuits.