Hardware based error and flow control in the Axon gigabit host-network interface

The primary goal of the Axon architecture is to support a high-performance data path delivering high network bandwidth directly to applications. The Axon network interface is described from the perspective of its simulation, and in particular and implementation of error and flow control in hardware. Background is provided on the simulation package that has been used to explore these mechanisms, and a brief overview is given of the Axon architecture is implemented by the simulator. The error control mechanism, the hardware design, and the functional and performance simulation results are outlined. The rate control scheme is described, along with its implementation and simulation.<<ETX>>

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