The novel high efficiency on chip transformers for the CMOS power amplifier

This paper proposes a novel on chip transformer for the purpose of combining output voltage of the high power amplifier in a standard 0.13-µm TSMC CMOS technology. The transformer adopts multi-finger architecture which provides low insertion loss and allows high current capacity on the transformer. The proposed transformer is estimated and designed by 3-D electromagnetic simulator. Due to the multi-finger structure, the voltage transfer efficiency from input to output at the transformer reaches 81%. To enhance linearity of the PA, cross coupled compensation capacitors are added. With all integration of transformers, baluns, and paralell 4 diff-amps, the prototype Class AB Power Amplifier shows 30dBm saturation power with 1.8V supply voltage and 35dBm with 3V supply voltage at 2.4 GHz. The output P1dB is 27dBm with 18% drain efficiency and 30dBm with 15.6% drain efficiency.

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