Optimization of silicon technology for the IBM System z9
暂无分享,去创建一个
Daniel C. Edelstein | Mukesh Khare | Gary B. Bronner | Shreesh Narasimha | Paul D. Agnello | Scott R. Stiffler | Jed H. Rankin | Daniel J. Poindexter | Philip T. Wu | Thomas Ivers | Thomas B. Faure | David A. Grosch | Marc D. Knox | Hyun-Jang Nam | Shahid A. Butt
[1] Edward W. Conrad,et al. Model-based verification for first time right manufacturing , 2005, SPIE Advanced Lithography.
[2] Wei Jin,et al. High performance 50 nm CMOS devices for microprocessor and embedded processor core applications , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
[3] M.B. Ketchen,et al. Ring oscillators for CMOS process tuning and variability control , 2006, IEEE Transactions on Semiconductor Manufacturing.
[4] Lars Liebmann,et al. TCAD development for lithography resolution enhancement , 2001, IBM J. Res. Dev..
[5] Baoqin Chen,et al. Proximity effect in electron beam lithography , 2004, Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004..
[6] J. Gill,et al. Reliability, yield, and performance of a 90 nm SOI/Cu/SiCOH technology , 2004, Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729).
[7] Frank E. Abboud,et al. Evaluation of OPC mask printing with a raster scan pattern generator , 2002, SPIE Advanced Lithography.
[8] M. Agostinelli,et al. 6-T cell circuit dependent GOX SBD model for accurate prediction of observed vccmin test voltage dependency , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.
[9] J. Gill,et al. Comprehensive reliability evaluation of a 90 nm CMOS technology with Cu/PECVD low-k BEOL , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.
[10] S.K. Iyer,et al. Electrically programmable fuse (eFUSE) using electromigration in silicides , 2002, IEEE Electron Device Letters.
[11] Jennifer Yario. 2005 top Fab: IBM , 2005 .
[12] S. Narasimha,et al. A high performance 90nm SOI technology with 0.992 /spl mu/m2 6T-SRAM cell , 2002, Digest. International Electron Devices Meeting,.
[13] S. Narasimha,et al. A high performance 0.13 /spl mu/m SOI CMOS technology with Cu interconnects and low-k BEOL dielectric , 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).
[14] H. Kimura,et al. RTA-Driven Intra-Die Variations in Stage Delay, and Parametric Sensitivities for 65nm Technology , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..
[15] H. E. Hamilton. Thermal aspects of burn-in of high power semiconductor devices , 2002, ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258).
[16] G. Burbach,et al. Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
[17] Gregory A. Northrop,et al. IBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology , 2002, IBM J. Res. Dev..
[18] P. Roper,et al. Full copper wiring in a sub-0.25 /spl mu/m CMOS ULSI technology , 1997, International Electron Devices Meeting. IEDM Technical Digest.
[19] G. Owen,et al. Proximity effect correction for electron beam lithography by equalization of background dose , 1983 .
[20] Edward J. Nowak,et al. Maintaining the benefits of CMOS scaling when scaling bogs down , 2002, IBM J. Res. Dev..
[21] C.-C. Yang,et al. Chip-to-package interaction for a 90 nm Cu / PECVD low-k technology , 2004, Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729).