We have introduced a new flash array architecture called AMG a t e r n a t e Metal virtual Ground) to address the high density and low voltage (3V only) applications. A 2.lpm2 cell size is demonstrated with 0.6pm design rules. A low current programming technique has been developed to enable low voltage operation. A segmented array architecture is introduced t,o eliminat,e cycling induced program-erase disturbs. An innovative planarized array DPCC (Double Poly Contact Circuit) process is developed to reahze the AMG architecture. INTRODUCTION In recent years, the feature size h is being scaled to realize the flash memory products [I] [ 2 ] . We'have realized a new flash virtual ground architecture [3] t,o provide a scaling pa th for high density and low voltage products. The cell size (5.8h2) scaling is obtained without the aggressive metallcontact design rules of the standard NOR (10h2) or the high voltage and access speed penalty of the NAND approach (6.5h2) [4]. Alternate Metal Virlual Ground (AMG) EPROM array concept [5] has been demonstrated in production as . a viable scaling concept with a poly pitch limited cell size (4x2) and one metal line for two diffusion bitlines. The AMG flash architecture is a scalable concept where the AMG cell can be scaled to 0.7pm2 with 0.35pm design rules. The array is a segmented virtual ground array with dedicated buried diffusion bitlines for program and erase operations. The programming and erase operations in the array are based on the well characterized standard NOR channel hot electron programming and negative gate source erase. Electron injection efficiency of the flash cell has been enhanced 161 in order to provide low current programming. AMG FLASH ARRAY The AMG flash array s c h e m h c is shown in fig.1 There are two h n d s of junctions for the diffusion lines in the flash cell area. The flash cell is programmed using channel hot electron programming a t the abrupt junction and erased with Fowler Nordheim tunneling a t the graded junction. The array is segmented with Block select BL SEL n and accomodates 128 WLs leading to the select area overhead of approximately 10%. The truth table for the array operational modes is summarized in fig.:!. The indlvidual cells are accessed by choosing the Block The select transistors are n-channel transistors with gate oxide of 200A . The integration in the array is made possible by utilizing the DPCC process 171. The select channel length tracks the flash cell poly length variations. This array architecture configures very naturally to wordhne block oriented sectorization for erase. The block selection feature offers advantages for disturb immunity, bitline capacitance reduction and sector erase, utilizing only single level metal in the array. AMG PROCESS FLOW The AMG flash process incorporates definition of minimum polyl pitch and minimum poly2 spacing. The process flow is summarized in fig. 3. In order to achieve minimum cell size a 3kA LOCOS field oxide is employed as a coupling enhancement oxide for the flash cell. It also provides high isolation for the parasitic select transistor. The thin field oxide results in a simpler self aligned oxide etch than the 6-7kA field oxide etch tha t is used for the standard Tshaped cell array [8]. The cell active area is defined in stripes along the wordline to avoid any two dimensional field oxide definition and misalignment effects on the cell gate coupling. The dlffusion bitlines are defined with a sclfaligned source etch with the polyl as a mask, to provide a polyl pitch limited cell in one direction. The cell is planarized before poly2 definition to improve polycide and self ahgned etch in the array [9][10]. The process is integrated with 2 layers of metal and WSiz poly:! gates. The TEM of the planarized AMG array is shown in fig. 4. LOW CURRENT PROGRAMMING In order to maximize the number of wordlines per AMG block we have engineered the cell for efficient low current programming by optimizing the channel doping and channel length. A ramped gate vollage technique is employed to further control the programming current, where the ramped gate reduces the programming current from 360pA to 180p.A. The ramped gate control maintains a high Vds during programming and minimizes the bitline resistance voltage drops. Implementation of this technique is demonstrated on a lMeg array and shown in fig. 5. The low current programming makes possible the scaling of the power supply to 3V without a big programming charge pump size penalty. ELECTRICAL ERASE The maximum tunnel oxide field and the band-band tunneling current are regulated by controlling the source and gate voltage levels during the erase algorithm. By floating the drain junction during the erase we have not compromised the reliability of the cell relative to a standard array. The reference cell read current typically is 25pA RELIABILITY RESULTS The AMG array reliability issues are the same as in the standard array. There is good margin for immunity from bitline and wordline disturbs during programming. The charge retention characteristics for both the programmed and erased cells are very good after 500hrs. a t 250'2. The read onented soft write d s tu rb is characterized and bitline voltage less than 1.4V ensures 10yr. immunity. The AMG flash cell has been cyclcd upto 105 cycles with acceptable programming and erase time degradation. (see fig.6) 67 4-93081 3-75-1 197 1997 Symposium on VLSl Technology Digest of Technical Papers