Binary adder circuit design using emerging MIGFET devices

Multiple independent-gate field effect transistors (MIGFETs) have great potential for digital integrated circuits. In this work, we demonstrate that conventional binary adder architectures may benefit from the use of MIGFET devices. As case studies, we have designed ripple-carry adders (RCA) and parallel-prefix adders (PPA), where circuit area and performance optimizations are explored. Different versions of adders have been built using MIGFET and compared to adder topologies based on single-gate transistors.

[1]  Tack-Don Han,et al.  Fast area-efficient VLSI adders , 1987, 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH).

[2]  Ralph K. Cavin,et al.  A Long-term View of Research Targets in Nanoelectronics , 2005 .

[3]  Giovanni De Micheli,et al.  An Efficient Gate Library for Ambipolar CNTFET Logic , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Giovanni De Micheli,et al.  New Logic Synthesis as Nanotechnology Enabler , 2015, Proceedings of the IEEE.

[5]  Harold S. Stone,et al.  A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.

[6]  H. T. Kung,et al.  A Regular Layout for Parallel Adders , 1982, IEEE Transactions on Computers.

[7]  Felipe S. Marques,et al.  Exploring independent gates in FinFET-based transistor network generation , 2014, 2014 27th Symposium on Integrated Circuits and Systems Design (SBCCI).

[8]  Niraj K. Jha,et al.  Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Tadashi Shibata,et al.  A functional MOS transistor featuring gate-level weighted sum and threshold operations , 1992 .

[10]  Giovanni De Micheli,et al.  Biconditional Binary Decision Diagrams: A Novel Canonical Logic Representation Form , 2014, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[11]  Chip-Hong Chang,et al.  Residue Number Systems: A New Paradigm to Datapath Optimization for Low-Power and High-Performance Digital Signal Processing Applications , 2015, IEEE Circuits and Systems Magazine.

[12]  Giovanni De Micheli,et al.  Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  Yusuf Leblebici,et al.  Configurable Logic Gates Using Polarity-Controlled Silicon Nanowire Gate-All-Around FETs , 2014, IEEE Electron Device Letters.

[14]  S. Vidya,et al.  GRAPH-BASED TRANSISTOR NETWORK GENERATION METHOD FOR SUPERGATE DESIGN , 2016 .

[15]  Kartik Mohanram,et al.  Dual-$V_{th}$ Independent-Gate FinFETs for Low Power Logic Circuits , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Giovanni De Micheli,et al.  Multiple Independent Gate FETs: How many gates do we need? , 2015, The 20th Asia and South Pacific Design Automation Conference.

[17]  Lars-Erik Wernersson,et al.  III–V compound semiconductor transistors—from planar to nanowire structures , 2014 .