Reliability compact modeling approach for layout dependent effects in advanced CMOS nodes
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F. Andrieu | M. Rafik | X. Federspiel | R. Berthelon | V. Huard | F. Cacho | A. Bravaix | C. Diouf | C. Ndiaye | S. Ortolland | R. Lajmi | F. Andrieu | V. Huard | X. Federspiel | M. Rafik | A. Bravaix | F. Cacho | C. Diouf | S. Ortolland | R. Berthelon | R. Lajmi | C. Ndiaye
[1] M. Rafik,et al. Layout Dependent Effect: Impact on device performance and reliability in recent CMOS nodes , 2016, 2016 IEEE International Integrated Reliability Workshop (IIRW).
[2] John V. Faricelli,et al. Layout-dependent proximity effects in deep nanoscale CMOS , 2010, IEEE Custom Integrated Circuits Conference 2010.
[3] Dimitris P. Ioannou,et al. Mechanical stress effects on p-channel MOSFET performance and NBTI reliability , 2014, 2014 IEEE International Reliability Physics Symposium.
[4] F. Andrieu,et al. Impact of the design layout on threshold voltage in SiGe channel UTBB-FDSOI pMOSFET , 2016, 2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS).
[5] Y. Nishi,et al. Experimental study of biaxial and uniaxial strain effects on carrier mobility in bulk and ultrathin-body SOI MOSFETs , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
[6] Runsheng Wang,et al. Layout dependent BTI and HCI degradation in nano CMOS technology: A new time-dependent LDE and impacts on circuit at end of life , 2016, 2016 International Conference on IC Design and Technology (ICICDT).
[7] A. Pofelski,et al. Design / technology co-optimization of strain-induced layout effects in 14nm UTBB-FDSOI CMOS: Enablement and assessment of continuous-RX designs , 2016, 2016 IEEE Symposium on VLSI Technology.
[8] J. Mazurier,et al. Static and dynamic power management in 14nm FDSOI technology , 2015, 2015 International Conference on IC Design & Technology (ICICDT).
[9] A. Mercha,et al. Layout-induced stress effects in 14nm & 10nm FinFETs and their impact on performance , 2013, 2013 Symposium on VLSI Circuits.
[10] Yao-Wen Chang,et al. Layout-dependent-effects-aware analytical analog placement , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).
[11] K. Maex,et al. Silicide induced pattern density and orientation dependent transconductance in MOS transistors , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).