Self-calibrating on-chip termination resistor for high-speed SerDes
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[1] T. J. Gabara. On-chip terminating resistors for high speed ECL-CMOS interfaces , 1992, [1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit.
[2] Shyh-Jye Jou,et al. Adaptive on-die termination resistors for high-speed transceiver , 2005, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT)..
[3] T. Knight,et al. Automatic impedance control , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[4] Heather Joan Conrad. 2.4 Gbit/s CML I/Os with integrated line termination resistors realized in 0.5 /spl mu/m BiCMOS technology , 1997, Proceedings of the 1997 Bipolar/BiCMOS Circuits and Technology Meeting.
[5] Yan Xiao-lang,et al. On-chip high precision terminating resistors for transmitter , 2003, ASICON 2003.
[6] J. E. Smith,et al. On-die termination resistors with analog impedance control for standard CMOS technology , 2003 .
[7] Mohammed Ismail,et al. A digital tuning algorithm for on-chip resistors , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).
[8] Li Hao-liang. A Novel High-Precision on Chip Termination Resistor Circuit , 2009 .
[9] Li Chang-qing. A Novel High-precision on Chip Termination Resistor Circuit , 2008 .
[10] M. Kumric,et al. Digitally tuneable on-chip line termination resistor for 2.5Gbit/s LVDS receiver in 0.25µ standard CMOS technology , 2001, Proceedings of the 27th European Solid-State Circuits Conference.