Measurement considerations for future high speed computer packaging

AbstractThe decrease in the cycle times of computers has resulted from improvements in the performance of the active circuits and thepassive structures on which these circuits are packaged. In this paper we first summarize the state of the art in high -performancecomputer packaging. Estimates of future requirements for package interconnection structures are then described along with a fewmeasurement techniques that can be used to characterize their electrical properties. High -speed measurements on an experimentalthin -film transmission line structure obtained using three of these techniques are presented to illustrate the different measurementconsiderations.IntroductionAs a result of the dramatic improvements in circuit speed and density provided by new integrated circuit (IC) technologies,package characteristics have become a major factor in determining computer system performance. With the projected enhance-ments in device and circuit speeds of advanced silicon ICs, continued decrease in the cycle time of digital computers will becomemore dependent on the performance of the structures on which these circuits are packaged. Packaging limitations are expectedto be even more severe for the higher speed GaAs device technologies.For a typical mainframe computer system, a large fraction of the cycle time is already due to the propagation delays introducedby wires interconnecting the semiconductor ICs which make up its logic and memory [1]. The package also contributes to variousundesirable phenomena such as pulse dispersion, reflections, crosstalk and switching induced noise, all of which limit the systemperformance which can be attained. Higher switching speeds place greater demands on the bandwidth of the package, and requirethat accurate models of package wiring characteristics be developed to aid in engineering an optimum design. High speed meas-urement techniques are required to adequately characterize such designs, and to refine the analytical models which are used topredict their behavior.In this paper, we concentrate on the problems of chip to chip interconnection wiring, and the various high speed measurementtechniques which are useful in characterizing its performance. We first briefly summarize the state of the art in high performancecomputer packaging, and present estimates of future trends in chip and package characteristics. We then survey the various highspeed measurement techniques which may be useful for characterizing the electrical properties of packaging structures. Finally,results obtained from the use of several high speed measurement techniques on an experimental thin film transmission line struc-ture are described.